EDN

VHDL 101 – IF, CASE, and WHEN in a Process

Last time, in the third installment of VHDL we discussed logic gates and Adders. Let’s move on to some basic VHDL structure. All HDL languages bridge what for many feels like a strange brew of ...
EDN

Designers debate ‘VHDL is dead’ assertion

SANTA CRUZ, Calif. — Recent reports of remarks by Aart de Geus, Synopsys CEO, stating that SystemVerilog will replace VHDL caused a torrent of commentary in Thursday's (April 24) E-Mail Synopsys Users ...