Design-Reuse

Dual edge sequential architecture capable of eliminating complete hold requirement from the test path

Freescale Semiconductor India Pvt. Ltd. Scannability has always been a challenge and with the complex architectures, challenges gets multifold by imposing several limitations like HOLD closure, yield ...
AZoNano

Researchers Find that the ‘Crossbar Latch’ Can Replace Transistors and Improve Processing Power

The often-quoted Moore 's Law says that we can expect processors to double in capacity every 18 months. And that has held true. Now computer scientists warn that - without some significant ...
Semiconductor Engineering

Transistor-Level Performance Evaluation Based On Wafer-Level Process Modeling

Three years ago, I wrote a blog entitled “Linking Virtual Wafer Fabrication Modeling with Device-level TCAD Simulation,” in which I described the seamless connection between the SEMulator3D virtual ...
Semiconductor Engineering

Transistor-Level Verification Returns

Technologies that had become specialist tools are moving back into mainstream usage; shift left is not just about doing things earlier in the flow. A few decades ago, all designers did ...